

module I_type(
    input [2:0] funct3,
    input bit_th,
    input signed [31:0] in1,
    input signed [31:0] imm,
    output reg [31:0] out
);

    //wire [4:0] imm_shift_amount = imm[4:0];
    wire [31:0] tmp1;
    wire [31:0] tmp2; 
    assign tmp1 = in1;
    assign tmp2 = imm;
    always @(*) begin
        case (funct3)
            3'b000: out = in1 + imm;
            3'b010: out = (in1 < imm) ? 1 : 0;
            3'b011: out = (tmp1 < tmp2) ? 1 : 0;
            3'b100: out = in1 ^ imm;
            3'b110: out = in1 | imm;
            3'b111: out = in1 & imm;
            3'b001: out = in1 << imm[4:0];   //imm_shift_amount;
            3'b101: //out = bit_th ? in1 >> imm[4:0] : in1 >>> imm[4:0];
            begin
                if(bit_th == 0) out = in1 >> imm[4:0]; 
	            else out = in1 >>> imm[4:0];
            end
            default: out = 32'd0;
        endcase
    end

endmodule

